1. Field of Invention
The present invention relates to the power consumption conservation of a processor, and in particular to a method for reducing the power consumption of a processor, which can reduce the power consumption of the processor while guaranteeing that the voltage of the processor meets application requirements.
2. Description of Prior Art
Limited battery lifetime usually becomes the most severe bottleneck in a processing system powered by a battery, such as embedded handheld system. On the other hand, playing of multimedia, especially video, has gotten increasing popularity with various handsets, such as PMP and PDA. This gives considerable importance to a low power consumption design for any battery-powered processing system. Moreover, in current handsets, embedded CPUs have been expanded in terms of performance and function, and thus can enable such operation as soft decoding. It is well known that soft decoding is an application requiring intensive processing by CPU and consuming plenty of battery power.
During video soft decoding by CPU, a low power consumption design is generally realized with a technique called DVS/DFS (Dynamic Voltage/Frequency Scaling). One significant task in the DVS technique is selecting a suitable CPU load sampling cycle and predicting CPU load through a proper algorithm so as to determine the magnitudes of voltage and frequency should be set in next time interval. As well known in the art, the selection of sampling cycle has tremendous effect on the performance of DVS. Currently, it is generally believed that the sampling cycle or interval should be the reciprocal of frame rate, since video stream is in unit of frame in most cases. Take as an example a segment of a stream of 30 frames/s, the sampling cycle or interval takes the value of 33 ms, which is regarded as the most suitable. However, many studies have proved that data of CPU load obtained on such sampling interval have a very poor regularity. Thus, it is difficult to present a satisfactory prediction result, leading to the case of voltage being lower than that required by the processor or the case of excessive power consumption of the processor.
Another critical issue in the above low power consumption design based on time interval is how to accurately predict next time interval, since the processor load varies with applications. For example, Reference document 1 (Xiaotao Liu, Prashant Shenoy and Weibo Gong, A Time Series-based Approach for Power Management in Mobile Processors and Disks, In Proceedings of the 14th ACM Workshop on Network and Operating System Support for Audio and Video (NOSSDAV)) proposes a time series-based prediction method, in which the value of processor load is predicted using time series. This method, however, gives no discussion about how to adjust the processor power dynamically. In other words, this method cannot precisely predict the value of processor load for next time interval upon changes in the running condition of the processor.